CHENNAI : ‘Digital India RISC-V Symposium’, a one-day event showcasing the ‘future of Electronics in India through the RISC-V pathway’ was organized today (6th August 2023) at IIT Madras Research Park.

The Symposium featured insightful tech talks by esteemed academics and industry experts, interactive stalls showcasing indigenous RISC-V processors, an engaging hackathon, and a special Investor meeting.

The Symposium was organized by the Ministry of Electronics and Information Technology, Government of India, IIT Madras and IITM Pravartak Technologies Foundation. Rajeev Chandrasekhar, Minister of State for Electronics and Information Technology, Government of India, participated virtually in the event. Prof. V. Kamakoti, Director, IIT Madras, took part along with researchers, professors and students.

The Government of India, taking concrete steps towards realizing the ambition of self-reliance and a momentous stride towards Atmanirbhar Bharat, launched the Digital India RISC-V Microprocessor (DIR-V) Program with an overall aim to create Microprocessors for the future in India, for the world and achieve industry-grade silicon and Design wins by December 2023. 

Addressing the Symposium virtually, Chief Guest Rajeev Chandrasekhar, Minister of State for Electronics and Information Technology, Government of India, said, “Less than a decade ago, India was a consumer of technologies. India was a large market that consumed technologies and innovations that were innovated outside of this country and we were on the edges of this core deep tech ecosystem of semiconductors, electronics and high performance systems.

It was in 2015, that this vision was laid out by our Prime Minister Narendra Modi that India must transform from a consumer of technologies to a country where our innovators and start-ups are architecting and designing platforms, solutions, systems, products and devices as much as any other nation in the world.

Here we are, 15 months after the SEMICON program was launched, we are now talking about the future of DIR-V (Digital India RISC-V) and how IIT Madras is fast becoming a hub for innovation, creativity and future systems around DIR-V.”

Congratulating Prof. V. Kamakoti for his leadership as the Chief Architect of DIR-V program and Krishnakumar Rao, Senior Director, CDAC Trivandrum, Rajeev Chandrasekhar added, “Between IIT Madras and CDAC, you are certainly becoming a beacon to all of the other academic institutions around the world who are interested in becoming part of this rapidly galloping ecosystem of semiconductors and electronics innovation. You are inspiring them to join this as well.”

Rajeev Chandrasekhar added, “The Government of India is very committed to making DIR-V the Indian ISA. While we may continue to have activities and programs in the x86/ARM space, we are almost all in the DIR-V Programs. All of the innovations and systems and technologies and capabilities that we need in the automotive IoT sensor space, mobility space and high performance computing space, our goal is to make sure that DIR-V has a serious presence in all of these three segments.”

The results of the RISC-V ‘Capture The Bug’ Hackathon, conducted by Vyoma Systems Pvt. Ltd., were also announced during the occasion.

Speaking on the occasion, Prof. V. Kamakoti, Director, IIT Madras, said, “Today is a very important event in the journey of semiconductors, which our country has embarked on. We started this journey during 2013-14 when we believed that there was going to be a major digital revolution that was going to happen globally and that many electronic devices were going to come closer to our lives.

Each of those devices would have a microprocessor and there must be a concerted effort where we make our own microprocessors for our country. We must make our indigenous microprocessor and we must know what it contains. We should be in a position to quickly configure and customize the microprocessors according to the requirement.”

Prof. V. Kamakoti added, “Berkeley and MIT started RISC-V and they made it open source under a BSD license enabling users to customize it per their own requirements without encumbrances. IIT Madras joined this initiative around 2014 and we have made a lot of progress. We are now on the cusp of releasing chips that can suit many requirements. Thanks to many initiatives of the Government, I am sure that within the next few months to a year, we will see prototype chips and products coming out of our own microprocessor.”

Speaking on the occasion, S. Krishnakumar Rao, Senior Director and Head (Hardware Design Group), CDAC-Trivandrum, said, “With the Government of India’s DIR-V Program initiative and the drive towards making ‘RISC-V’ as the Indian ISA, we have made significant progress. Along with IIT Madras, Academia, with start-ups and industry coming on-board we see a lot of traction in the coming years and are confident that we will have a lot of RISC-V based silicon and real products coming out from India.”

Addressing virtually, Calista Redmond, CEO, RISC-V International, said, “Open standards and collaborations are strategic to hardware and software across industries and geographies. For generations, decades upon decades, we have relied upon only two architectures and now, RISC-V is a formidable third. RISC-V is our collective opportunity around the world to unleash creativity and embark on innovations.

That ushers in economic growth for all of us, including India. There are three main reasons why RISC-V is poised to be so successful – As the most successful architecture in history, we are on course to be inevitable across all work loads. We are also enabling the best processors, this is by design because you have full transparency and control and innovations over the innovation that you can bring to the workload challenge.

No hardware acts alone in isolation. We need an entire ecosystem of IP design, software providers, and all stakeholders that are engaged in this community, from engineers early in their studies to multinationals who have already established positions across the world.”

The basic component of a processor is its ISA (Instruction set architecture). It is known that all processors have both hardware and software. While the hardware part of the processing component is fundamentally dependent on physical elements such as gates, transistors, clocks, memory, interconnect peripherals, semiconductor technology nodes etc, the software development is highly inspired by the end-user application scenario. A processor’s ISA determines where and how this software and hardware meet and what the interface should be, and thus, the fundamental design of the processor itself.

Unlike the heavily stifling, proprietary closed and licensed ISA-based approach followed by other processors in the market, which usually targets general-purpose applications, RISC-V-based processor designs are inspired by domain-specific applications. RISC-V ISA license is free, open source, modular, addable, scalable, and customisable and thus can scale from processors for simple microcontrollers [for small embedded applications] to purpose-built Cyber-Physical Systems to tiny IOT/WSN devices to cloud computing platforms to High-Performance Computing systems for both scientific and ML training. RISC-V ISA is free and it enables a new era of processor innovation through open standard collaboration.

Sensing this non-stifling enormous opportunity that can be leveraged by the startup-entrepreneurship initiatives, especially from the student community, the Digital India RISC-V Symposium is the first-in-line tech symposium focussing exclusively on RISC-V based product design road map and opportunities for Electronics in India.